This invention relates to a proximity correction system for use in wafer lithography, the processing step in semiconductor manufacturing in which circuit design pattern layouts are transferred to the wafer.
Wafer lithography is the processing step in semiconductor manufacturing in which circuit design pattern layouts are transferred to the wafer. During wafer fabrication the physical shapes of circuit elements tend to be distorted. This distortion causes a loss of yield in wafer production because some of the elements do not function. Even if the elements function, the distortion can cause a loss of circuit performance.
The wafer fabrication process involves a series of principle pattern transfer steps including, but not limited to, thermal oxidation or deposition, masking, etching, and doping. In the additive step of thermal oxidation or deposition the wafers are prepared by cleaning, heating, and oxidation. In the masking step, one area of the wafer is protected while another area is exposed. One type of masking is optical lithography in which a metallic coated quartz plate (known as a photomask) having a magnified image of the desired pattern etched into the metallic layer is illuminated. The illuminated image is reduced in size and patterned into a photosensitive film on the device substrate. The etching step is a subtracting step that sets the pattern. In the doping step the pattern is treated so that the pattern has the proper electrical characteristics.
As a result the steps of the pattern transfer, images formed on the device substrate generally deviate from the ideal dimensions of the desired pattern. These deviations or proximity errors may be caused by, among other things, distortions in optical proximity (generally caused by imperfect lenses), varying resist thickness over topography, micro-loading (caused by interactions between chemical activity sites), and light scattering and reflection. In other words, these deviations depend on the characteristics of the patterns as well as a variety of process conditions.
The above mentioned deviations are comprised of both random and systematic components. Random deviations derive from mechanisms based on uncertainty or chance. Systematic deviations, by definition, originate from irregularities in the lithography system. When system states remain constant, systematic errors will repeat. Therefore, systematic errors can be compensated by making offsetting adjustments. There is no way to offset random errors a priori, but there are ways to tighten their distributions with compensation methods.
The methods used to correct errors can be lumped together generally as "correction methodology" in which the complete original chip layout description is used to create a complete corrected chip layout. There are many types of correction methodologies, however, this patent will focus on pattern inversion methods that simulate pattern segments to determine what the features will look like on the fabricated wafer, then, compute adjustments to the pattern shapes based on the difference between the simulated wafer image and the original pattern. Pattern simulation provides a prediction of what the drawn figures will look like on the wafer. Two-dimensional convolution is a key computational element of one type of pattern simulation. Convolution kernels, representing a model of a wafer process, are convolved with the pattern shapes to predict the wafer image.
Proximity correction techniques (or pattern correction methodology) compensate pattern distortions by calculating "inverse" feature shapes (or pattern inversions) to apply to the photomask. When the inverse shapes undergo the expected distortions, shapes actually transferred to the wafer will be true to the "drawn shapes." Constructing inverse shapes typically involves biasing feature edges by an amount dependent upon their local configuration environment.
Key elements of proximity correction technology are the methods for predicting process distortions, and methods for calculating the inverse feature shapes. One type of proximity correction methodology, "rules-based," uses geometric measurements, such as line width and space width, to estimate local configuration environments at every point along feature edges. These width and space measurements are used as indices to a table of "rules" which contain predetermined edge-biasing values. Another type of proximity correction, "model-based," simulates the shapes expected on the wafer, and computes adjustments to the pattern shapes based on the difference between the simulated wafer image and the original pattern. Discussions of model-based proximity correction can be found in "Wafer Proximity Correction and its Impact on Mask-Making" by John P. Stirniman and Michael L. Rieger (BACUS News Photomask, Volume 10, Issue 1, pages 1-12, January 1994), "Optimizing proximity correction for wafer fabrication process" by John P. Stirniman and Michael L. Rieger (14th Annual BACUS Symposium on Photomask Technology and Management, Proc. SPIE 2322 1994, pages 239-246), and "Fast proximity correction with zone sampling" by John P. Stirniman and Michael L. Rieger (Optical/Laser Micr. VII, Proc. SPIE 2197 1994, pages 294-301).
FIGS. 1A and 1B show a system for applying wafer proximity correction. First an original drawn shapes or design layout 10 is created (an example of an original pattern is shown in FIG. 12A). Second, as shown in FIG. 1A, the layout pattern 10 is etched into a standard mask 12. The pattern 10 is then captured on a wafer using the above described lithography process during which the pattern 10 is subject to optical effects 14, resist effects 16, and etch effects 18. The result is an uncorrected wafer structure 20 with the deviations discussed above (FIG. 12B shows the original pattern with an uncorrected wafer structure overlay). From the deformations in the uncorrected wafer structure 20, the type of wafer proximity correction needed for this specific set of optical effects 14, resist effects 16, and etch effects 18 is determined. Using this information, as shown in FIG. 1B, the design layout 10 is subjected to wafer proximity correction 30. A corrected mask 32 is then formed that is designed to correct the deformations. Using the corrected mask 32 in the above described lithography process, the pattern 10 is subjected to the same optical effects 14, resist effects 16, and etch effects 18. The result is a corrected wafer structure 40 with significantly fewer deviations.